Design a FSM which takes a stream of bits considering that the MSB is the first to come, and the output is ‘1’ if the number that accumulated this far is divided by 5.

Hello,
I have some difficulty understanding the details of the question
Is it possible to assume that the register is infinite and initialized at zero? Maybe an example will help Thank you

You don’t need to assume infinite register.
You can look at this example of how to generate the actual circuit from the FSM: http://logic-quest.com/219-2/
Because the FSM has five states you will need at least three registers.

Hi,
First of all, Thank you very much for the reply.
But I think my problem is more in creating the FSM as required
I can not really understand how the bits get to the register – if I do not know the size of the register.
Is it possible to give an example for illustration?
Thank you,
Shani

You can think of a black box with X as an input. At each positive clock edge X is sampled with 0 or 1. The internal logic of the black box is generated from the FSM above. The main goal of the internal logic of the black box is to decide at each clock cycle if the stream of bits that accumulated this far is divided by 5 or not.

Now, for generating the FSM we need to write down some divided by 5 binary numbers. Simple example, the binary stream 000 is obviously equal to 0 in decimal, hence we are at state S0 and the output is 1. Then we can get the stream 101. When we see 1 we canâ€™t stay at state S0 and therefore we have to proceed to state S1 and the output is 0. When we see the second 1 we accumulated 000101 this far (5 in decimal) and we back to state S0 and the output is 1. In order to complete the full FSM we need to write down divided by 5 binary numbers and follow the pattern.

Hello,

I have some difficulty understanding the details of the question

Is it possible to assume that the register is infinite and initialized at zero? Maybe an example will help Thank you

You don’t need to assume infinite register.

You can look at this example of how to generate the actual circuit from the FSM:

http://logic-quest.com/219-2/

Because the FSM has five states you will need at least three registers.

Hi,

First of all, Thank you very much for the reply.

But I think my problem is more in creating the FSM as required

I can not really understand how the bits get to the register – if I do not know the size of the register.

Is it possible to give an example for illustration?

Thank you,

Shani

You can think of a black box with X as an input. At each positive clock edge X is sampled with 0 or 1. The internal logic of the black box is generated from the FSM above. The main goal of the internal logic of the black box is to decide at each clock cycle if the stream of bits that accumulated this far is divided by 5 or not.

Now, for generating the FSM we need to write down some divided by 5 binary numbers. Simple example, the binary stream 000 is obviously equal to 0 in decimal, hence we are at state S0 and the output is 1. Then we can get the stream 101. When we see 1 we canâ€™t stay at state S0 and therefore we have to proceed to state S1 and the output is 0. When we see the second 1 we accumulated 000101 this far (5 in decimal) and we back to state S0 and the output is 1. In order to complete the full FSM we need to write down divided by 5 binary numbers and follow the pattern.

I hope this helps.

http://logic-quest.com/wp-content/uploads/2022/03/f5.png

Thank you

The explanation was very helpful

I was able to find the right answer