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Clock Frequency Divider by 4

Design a clock frequency divider by 4.

Answer

The requested waveform:

Define the states and use karnaugh map:

Comments (4) on “Clock Frequency Divider by 4”

  1. Shani says:
    March 27, 2022 at 3:35 pm

    Hi,
    My solution to this question is different
    The reason for this is the output of the present state 11
    I do not quite understand why the output is 1 and not 0
    After all, we have to count 4 cycles of the original clock in order to complete a single cycle of the required clock.

    Thank you
    Shani

    Reply
    1. Logic-Quest says:
      March 27, 2022 at 9:02 pm

      We are looking for 50% duty cycle.
      Try to think how a wave diagram would look like if the output of state 11 is 0.
      I am attaching such a wave diagram:
      http://logic-quest.com/wp-content/uploads/2022/03/f4.png

      Reply
  2. Shani says:
    March 29, 2022 at 7:37 pm

    Hi,
    Thank you very much for the reply
    But I think I’m missing something along the way
    When I approach the question I draw the desired wave diagram. Then create a truth table based on the wave diagram I created
    According to the truth table, I know how to create the circle
    Unfortunately, it is difficult for me to understand how the wave diagram you created is obtained
    I would like any help given Thank you

    Reply
  3. Shani says:
    March 29, 2022 at 7:38 pm

    Hi,
    Thank you very much for the reply
    But I think I’m missing something along the way
    When I approach the question I draw the desired wave diagram. Then create a truth table based on the wave diagram I created
    According to the truth table, I know how to create the circle
    Unfortunately, it is difficult for me to understand how the wave diagram you created is obtained
    I would like any help given
    Thank you

    Reply

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