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Clock Frequency Divider by 3 with 50% duty cycle

Design a clock frequency divider by 3 with 50% duty cycle.

Answer

The first thing we want to do is to draw a wave diagram which describes the requested above.

We can start by designing a simple mod-3 couter and then we will try to manipulate it to generatre the above.

The following wave diagram is describing the behavior of this circuit:

We can notice that we are not far from the expected result. The output of the circuit is 33% duty cycle. In order to get 50% duty cycle, we need to connect this output into neg-edge Flop. The output of the nege-edge Flop can be seen down below

All is left to do is to XOR between the neg-edge output to its own input and we get clock divider by 3 with 50% duty cycle.

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