Design a synchronous system with input of on bit x, and an output of y. We define V(t) as the numbers of ‘1’ the system got until time t, and U(t) as the number of ‘0’.

The output of the system is ‘1’ if V(t) – U(t) =3k while k = 0,1,2…

We will define three states that will represent the remainder of the number V(t) – U(t) entered thus far divided by 3.
S0 – reminder 0
S1 – reminder 1
S2 – reminder 2
We will build the FSM:

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